• Fibre-Channel  PHY Solution Requires an advanced Very High Speed Serial Front-End. Our Multi-Gigabit Serial Link Solution includes All the blocks Necessary for this purpose. These blocks consist of High Speed Drivers, Clock Recovery DLL, PLL Architecture,  Serializer/Deserializer (SERDES), Low Jitter PECL and Comma Detect for Data Alignment.

SMS3000 Transceiver PHY has the following features:

•   1.065 Gigabit/s ANSI X3T11 Fibre Channel Compliant
•   10Bit Controller interface for receive and Transmit data paths
•   Inherently Full Duplex Operation
•   PECL Reference Clock option
•   Frequency comparison and auto-lock to reference
•   Programmable Receive Cable Equalization
•   Requires No External Loop Filter Capacitors
•   Transmit Jitter and distortion minimization through programmable transmit equalizer
•   Embedded Bit Error Rate Testing (BER) Through PBRS Generation and Detection
•   Proprietary Phase Detector allows superior receive jitter performance
•   Driver Compatible with Both 75 and 50 Ohm terminations
•   Full Low Cost, Low Power CMOS Implementation

SMS3000 Fibre-Channel Transceiver Data Sheet

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