Innovative Solutions for the emerging LAN/WAN & Broadband Markets

  1394 Transceiver  USB 2.0 USB2.0 PHY UTMI

Soft Mixed Signal Corporation utilizes Hard-Wired DSP Engines in its Mixed-Signal Transceivers. These Hard-Wired DSP Blocks are proprietary designs which are implemented in house as building blocks for DSP systems to be integrated with Analog Front End blocks for Transceiver implementations.

Eye diagram QAM CAP 16 constellation equalizer convergence high SNR

Two Dimensional Eye Diagram for QAM/CAP 16 Constellation showing the output of the equalizer during convergence with high SNR

These Hard-Wired DSP blocks are optimized for a combination of speed, area and power metrics which would satisfy the requirements of specific Transceiver.

  • FIR, IIR, Kalman Filter Implementations

    These filter types are the basic building blocks of all DSP systems. There are many ways of implementing all these filters which gives us the ability to configure the implementation for speed, and or area.


  • Adaptive Filters: LMS, CMA FIR filters

    Most DSP Systems are adaptive. The Error Criteria of adaptation decides what the filter is called. LMS and CMA are used mostly for their low hardware cost implementation and ease of analysis.

    LMS Adaptive Equalizer can be implemented with Pipeline in Update. The forward calculation block consists of Booth Multipliers merged with Multi-Input Adder. The Multi-Input Adder is a Wallace Tree Adder with 4-2 Compressor. For Performance reasons Custom 4-2 Compressor Cells are implemented at Circuit Level and Characterized by HSpice.

  • Trellis Coded Modulation Coders & Viterbi Decoders.

    To combat noise and ISI distortions of channels, TCM coding and Viterbi decoders are used. These advanced techniques give us the ability utilize the near optimal capacity of the channel predicted by Shannon's Theorem.


  • Fully Digital Clock Recovery

    Timing Detector using 2x Oversampled ADC. 
    ADC clock is non-synchronous to Transmit Clock. 
    Data Recovery done using Digital Interpolation. 
    Initial Filter Development In Matlab language. 
    Data-Path Optimization of Kalman Filter in Verilog RTL. 
    Polynomial Based Farrow Interpolator 
    Polynomial Coefficients Optimized with AMPL Script 

  • Reed-Solomon Forward Error Correction Coding/Decoding implementations

    Forward Error Correction is another way to increase the reliability of channels.

  • Coordinate transformation Algorithm using CORDIC Sine/Cosine in Verilog

    Area Optimized CORDIC unit for Sine/Cosine Calculation for Complex Value Magnitude Calculation

  • Verilog and VHDL RTL Design

    Most of our Designs are Implemented In HDLs. We selectively implement performance or power sensitive blocks using Full-Custom CMOS Design Methodology to meet Area/Power/Speed requirements.

Copyright 2003 by Soft Mixed Signal Corporation

  SMS Fully Integrated Gigabit Ethernet & Fibre Channel Transceiver Core is available
SMS announces OC-3/12 Transceiver Core
SMS UTMI Compliant USB2.0 (USB 2.0) PHY Core is available
SMS announces 10Base-T / 100Base-TX DSP Fast-Ethernet Transceiver IP
ATI's IXP family of integrated communications processors to include USB 2.0 technology from Soft Mixed Signal Corporation