Soft Mixed Signal Corporation develops and markets high-level, selective application and market oriented, complex Mixed Signal functions in the form of mega-function designs and system level ICs. The offered functions have high intellectual property in Analog/Mixed Signal design and DSP technology. With this system level expertise, users can have access to high-level complex functions for complete system solution and flexible design methodology for easy integration with industry standard Pure Digital CMOS Processes. The company has extensive expertise in WIDE AREA and LOCAL AREA NETWORK Technologies. SMS provides leading edge solutions for high volume, industry wide standards based vertical market areas in the form of Soft Mixed Signal Functions. The expertise, experience and system knowledge have been acquired in target areas along with close interface and interaction with industry groups and system developers/vendors. High growth markets that SMS specifically targets are:

• HIGH - PERFORMANCE LAN / WAN COMMUNICATIONS.
• SPECIALIZED SERIAL BUS & CLOCK GENERATION AND SYNCHRONIZATION.

SOFT MIXED SIGNAL CORPORATION, is a high-technology start-up company developing and marketing system level mixed signal integrated circuits for the newly emerging high-performance LAN, WAN and High Speed Serial Link markets, mainly OC-3, OC-12, OC-48 Transceivers, Gigabit Ethernet and 10-Gigabit Ethernet, High Speed Serial Link Applications such as Fiber Channel, Infiniband, DSP Based Fast Ethernet (100Mb/s 100B-TX), xDSL derivatives: ADSL/VDSL/HDSL and Cable Modem PHYs.

We are experienced in SONET, Ethernet, Fast Ethernet, Full Custom Communications IC development, Mixed signal PMD development for high speed (100Mb/s and over ), Digital System Architecture, DSP for data-communications and Clock/Data Recovery Systems. The developments are focused in high-performance Analog, DSP and Networking Architectures for LAN/WAN markets.

Soft Mixed Signal Corporation has been involved in developing specific designs to address these markets and applications. In addition to the system expertise being developed, the company has developed analog design methodologies, specific circuit topologies and techniques and layout methods that enable it to utilize industry standard Digital CMOS processes to implement these designs. Traditional analog circuit techniques generally require more expensive and special processes (Bipolar, BiCMOS with double poly, thin film requirements etc.) and do not lend themselves for large-scale integration due to methodology, cost, low yields, etc. In our design methodology we employ fully differential topologies, self-compensating stages with no additional capacitor compensation requirements, noise immune mixed signal topology in digital VLSI IC environment and self-calibration for process variations. We offer these functions in the form of technology independent mega-cell blocks.

In addition to the above features, every function that we develop has the complete testability provided through embedded test structures and necessary generic test programs and algorithms. The physical design contains necessary multiplexing, isolating, scanning, etc to examine each particular block. The designs are also accompanied by HDL (Verilog or VHDL) model descriptions to enable them to be incorporated into large VLSI components or used in system level simulations for board level designs. These models accurately describe the digital interface functionality and somewhat less accurately the analog behavior of the function, but provide enough information for high level functional simulations.

We have already developed the following core technologies based on pure digital CMOS process technology with 0.13um to 0.5um design:

• FULLY DIFFERENTIAL EQUALIZERS, FILTERS

                Proprietary CMOS analog adaptive equalizers up to 155Mb/s. Butterworth/Elliptic filters up to 7th order, 30Mhz employing GM and current mode continuous time.

• DIFFERENTIAL HIGH-SPEED DATA CONVERTERS FOR COMMUNICATIONS AND MULTIMEDIA

                Flash/pipeline A/D, video DAC, Sigma-Delta ADC/DAC.

• FULLY DIFFERENTIAL ARCHITECTURES FOR NOISY DIGITAL ENVIRONMENTS, NOISE IMMUNE CIRCUIT DESIGN AND LAYOUT TOPOLOGIES.

• PROPRIETARY HIGH-SPEED (3V/5V IO Tolerance AND UP TO 3.125 Gb/s) CLOCK RECOVERY.

• HIGH SPEED DSP CORES FOR QAM (CAP-16/32/64 COMPATIBLE ) & QPSK SIGNALING with ADC, DAC, AGC, CARRIER & CLOCK RECOVERY AND ALL ANALOG INTEGRATED FUNCTIONS.

• EXPERTISE IN CHANNEL/BUS MODEL DEVELOPMENT: TWISTED PAIR, COAX, FIBER, SERIAL/PARALLEL BUS ELECTRICAL CHARACTERISTICS.

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